The present invention relates to digital computer systems which provide multi-threaded execution. Specifically, a translation look-aside buffer (TLB) is provided which reduces the number of entries in the main memory required to service a multi-threaded computer system.
In order to increase the overall speed of computer program execution, multi-threaded computer processing units execute a plurality of threads associated with the program at one time. The execution of the program is divided into multiple threads which are active at the same time, and various hardware resources of the processor can simultaneously execute the active threads. Simultaneous processing of multiple independent instruction streams keeps the processors computational hardware resources active. Improved execution efficiency results and normal pipe-line stalls that may occur with a single threaded processor which are precipitated by instruction dependencies can be avoided with multi-threaded computer processors.
High performance multi-threaded processors have instructions from multiple threads which are in progress at the same time in different parts of the execution pipe line. Each of the threads is identified as a context and is allocated physical storage elements to hold the state associated with the thread. In any one instance, there is a physical register to hold an executing thread's architectural context. In this way, the various processes being executed are tagged with a thread ID, so that the computing results associated with each thread context can be applied to the correct architectural resources in the multi-threaded system.
In both single threaded processors and multi-threaded processors, memory management is necessary so that the program can retrieve values stored in a memory relatively quickly. A common technique used in memory management employs a look-aside buffer (TLB) which caches address translation key pairs. The TLB is generally a content addressable memory (CAM) having a virtual address as its look-up key. Program execution identifies a virtual address which is translated by the look-aside buffer (TLB) to obtain a real address of a memory location of a value needed for the program thread execution.
Entries in the translational look-aside buffer (TLB) are generally organized so that a virtual page number identified from code execution identifies a real page number stored within the memory. The TLB identifies from a virtual page number a group of pages, starting at a location identified by the virtual page number (VPN). The location within the group of pages is identified by the lower order bits of the virtual page number to save space in the look-aside buffer (TLB). This is important, in that the translational look-aside buffer (TLB) is a hardware table with a fixed capacity and if the CPU uses more pages of memory than the number of TLB mapping cache entries, the TLB will have to be updated from an external memory. The process of accessing the external memory and obtaining updates slows down the memory management process, and thus the overall relative speed of execution. With many threads running on the CPU nearly simultaneously, each of the active threads must keep a set of active mappings in the translational look-aside buffer (TLB) to avoid any significant penalty from fetching the mappings that are not resident in the TLB. Unfortunately, increasing the number of entries in the translational look-aside buffer (TLB) increases the required chip area and increases the access time and power consumption of the translational look-aside buffer (TLB).
It is therefore desirable to organize the contents of the translational look-up buffer (TLB) to reduce the need for frequent updates of the stored information without increasing the total number of memory locations available for translational data.